ToolBB-0104

neorv32-mcp: debug a NeoRV32 RISC-V soft core on an FPGA over UART and JTAG

neorv32-mcp offers 15 tools in two MCP servers for a NeoRV32 RISC-V core on an Alchitry Pt V2 FPGA board. UART tools load an ELF into RAM or flash it to SPI; OpenOCD tools halt the CPU and read memory. Flashing is refused unless the same ELF ran from RAM first, checked by SHA-256. The README shows no test logs.

Open original source github.com · greg676

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Briefing

The UART tools move the core between firmware and bootloader and read the end of each response to detect its state, so stale buffer contents do not mislead them. A recover tool flashes a known-good image and boots back to firmware, and a release tool frees the port for screen or the Alchitry IDE. The JTAG tools reach OpenOCD over telnet on port 4444 through the author's PicoDualProbe, described as a $5 probe.

A status file in the repo, dated 22 June 2026, reports that loading from SPI flash returned ERROR_DEVICE and that tool parameters were not reaching the server through its OpenAPI bridge. The quick start calls a script from a separate ai-design-studio project that the repo does not include.

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Repository facts

Repository facts for greg676/neorv32-mcp, from the GitHub API
Repositorygreg676/neorv32-mcp
Stars0
LanguagePython
Last push30 Jun 2026 3 mo ago

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