Area
Verilog, VHDL and SystemVerilog written or debugged by an agent, from simulation to synthesis on a real FPGA.
The most active tools first.
34 d ago
efinity-mcp drives a local install of Efinix's Efinity FPGA toolchain from an MCP client such as Claude. Its tools create projects and compile them, set up I/O and PLLs, read timing and utilization reports, and program boards over JTAG or SPI flash. The README says an assistant-built LED demo ran on a Ti375 dev kit. Only Windows is tested.
4 mo ago
oscilloscope-mcp connects Claude Code, Cursor or a custom agent to a Rigol DS1000Z oscilloscope over LAN SCPI. A profile lists the series' 15 trigger types and about 95 parameters, and the server checks requests against it before sending. A compare tool diffs captured edges against an RTL simulation. The README shows an agent-configured four-channel capture on a DS1104Z.
5 mo ago
Active Firmware Tools connected Claude Code to its Active-Pro logic analyzer and firmware debugger through an MCP server over TCP. In the two-minute video the agent triggers a capture on a custom board with three FPGAs running RISC-V soft cores. It reads firmware trace output alongside RGMII, USB enumeration and SCSI traffic and checks it for errors.
3 mo ago
neorv32-mcp offers 15 tools in two MCP servers for a NeoRV32 RISC-V core on an Alchitry Pt V2 FPGA board. UART tools load an ELF into RAM or flash it to SPI; OpenOCD tools halt the CPU and read memory. Flashing is refused unless the same ELF ran from RAM first, checked by SHA-256. The README shows no test logs.
Ranked by points weighed against age. New entries with early votes rise.
35 d ago
Felipe Sens Bonetto used AI agents to write openTPU, an LLM inference accelerator with its own instruction set, simulator, compiler and host software. On an Inspur PCIe card with a Xilinx Kintex-7 and 2 DDR3 channels it runs 10 models, including Qwen3 and Gemma 4, with their real weights. A README GIF shows the chat demo running on the card.
41 d ago
Munetomo Maruyama had Claude Code design mmRISC-2, a 64-bit RV64GC RISC-V core, and brought it up on a Digilent Arty A7-100T. Claude wrote the specification, SystemVerilog RTL, testbenches and documents; Maruyama ran Vivado and the board. Bring-up logs in the repository record Linux 7.2 booting to a shell at 50 MHz and a 120-minute stress test passing.
2 mo ago
In an Octopart video, one prompt sends Claude Code through a digital low-pass filter on a Digilent Cmod S7 FPGA board. It writes and simulates the filter, then programs the board over JTAG. Through MCP servers for an Analog Discovery 2 and a Rigol scope, it sweeps test tones at 1, 5 and 15 kHz against the 10 kHz cutoff.
29 d ago
AMD introduced Ross on 30 September, an agentic assistant for development on its FPGAs, adaptive SoCs and embedded x86 processors. AMD says Ross pairs MCP servers for its tools such as Vivado and Vitis HLS with expert-written agent skills and a documentation search. It runs in clients such as Claude Code or Cursor. The launch video shows no hardware run.
4 mo ago
Craig Hollabaugh had Claude Code boot Linux overnight on an Icepi Zero, a Lattice ECP5 FPGA board with no hard CPU. The agent installed LiteX and built a VexRiscv soft core that boots OpenSBI, Linux 5.14 and BusyBox to a root shell over USB serial. The 10-minute video logs into the running system on the board.
43 d ago
Lattice Semiconductor released Lattice Prompt, a free MCP link between agentic IDEs such as Claude Code or Cursor and its Radiant FPGA software. Lattice says an agent can run simulation, synthesis, place and route, timing analysis and bitstream generation from plain-language requests, grounded in its datasheets. The 16 September release reports productivity gains of 10x or more without a benchmark.
3 mo ago
In an Octopart video, Ari Mahpour gives Claude Code one prompt and an attached Analog Discovery 2. Running Opus 4.8, it upgrades a Vivado 2018 design to 2025.2 and programs a Digilent Arty A7 in about 15 minutes. Mahpour then saves the session as a CLAUDE.md file and skills; a fresh session repeats the bring-up in seconds.
3 mo ago
The FPGA Developer blog describes giving Claude Code control of programming, UART and power cycling on an AMD FPGA bench. In the post's example, the agent ports a reference design to a new dev board, then tests and fixes it there. The author says such ports take a few hours. The post also covers token use and hooks.
5 mo ago
Dimdim had Gemini 3.1 Pro write the Verilog for an audio reclocker on a MAX 10 10M08 board. He pasted code from the chat into Quartus. The design passes I2S through a dual-clock FIFO, adds DSD and S/PDIF input and buffers in PSRAM. Gemini, Claude Sonnet 4.6 and Claude Opus 4.7 all failed to make a PRBS-15 test work.
