Briefing
The first test chain used an Amanero board as the I2S source and an ES9023 DAC as the receiver, at 44.1 kHz and 32 bits, with PLLs deriving the clocks from the 50 MHz system clock. A 10 kHz test sine came out as junk on the scope. After Dimdim described what he saw, the chat suggested changes and the sine came out clean.
The PSRAM buffer over QSPI did not work at first. He had the design split into parts that could be tested alone, then found the faults by injecting known signals and watching them on a Saleae analyzer; he writes that the buffer now holds 64 Mb bit-perfectly. A knockoff USB Blaster never worked. The project took about 20 days, and a custom PCB is next.
Written by the Boards & Bots curator
“All that without me having to write a single line of Verilog code.”