Briefing
The core is an 8-stage in-order pipeline with an Sv39 MMU, a pipelined FPU, 16 KB L1 caches, a 256 KB L2 and hardware cache coherence for DMA. Peripherals come from LiteX. The README names Claude Sonnet 5, Opus 5 and Opus 5.5 as the models, used from 13 September to 19 October.
BRINGUP.md records each round on the board: where it stopped, the cause and the fix. Linux first reached a prompt on 25 September, after a new DMA port and data-cache fixes found in simulation. The final Rev.02 release adds Debian 13 with gcc compiling on the board and reports 2.794 CoreMark/MHz under Linux.
A white paper in English and Japanese evaluates the AI-driven process.
Written by the Boards & Bots curator
“The author set the goals, chose among the options it proposed, and ran Vivado and the board, passing the results back to it.”
From the GitHub API
Repository facts
| Repository | munetomo-maruyama/ |
|---|---|
| Stars | 73 |
| License | Apache-2.0 Permissive |
| Language | SystemVerilog |
| Last push | 16 Oct 2026 13 d ago |